Why does the example design simulation fail when the UniPHY controller is generated with PHY only option? - Why does the example design simulation fail when the UniPHY controller is generated with PHY only option? Description When simulating the example design of a UniPHY controller with PHY only option, some ports in the controller *_e0_c0 instance are not connected, causing the simulation to fail. Resolution The workaround is to tie all unconnected input ports to zero in the *_example_sim_e0_c0 instance of the *_e0.v file. This issue has been fixed in the Quartus® II software 13.1 version. Custom Fields values: ['novalue'] Troubleshooting 2205801576 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] 13.1 12.1 ['Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']