Introduction to the Nios® V Processors - This instructor-led class is taught in a virtual classroom for 1 half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training and pre-configured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. Course Description The Nios® V processors are the next generation 64-bit soft core processors based on the open-source RISC-V instruction set, designed for Altera® FPGA devices. A soft processors can be instantiated in a device’s programmable fabric allowing designers to add a microcontroller or microprocessor core to a solution, Nios V processors IP can be added through the device’s programmable fabric using Quartus® Software and Ashling RISCFree IDE for Altera® FPGAs. Course Objectives At course completion, you will be able to: Create a design using Nios V IP in Quartus Software Platform Designer. Understand the architecture and characteristics of Nios V processors and their variants. Program with software building tools a development kit to use Nios V processors. Understand the development flow for system design with Nios V processors. Practice during the hands-on lab exercises the use of different software tools and commands that will build the complete project for a Nios V processors applications. Skills Required Basic programming skills If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_INIOS. FPGA_INIOS. <p>Introduction to the Nios V Processor</p>