How do I preload the UniPHY-based memory model during RTL simulation? - How do I preload the UniPHY-based memory model during RTL simulation? Description When you generate the example design for the UniPHY-based external memory controllers, a generic memory model is created. This memory model has a memory array that can be preloaded with known values using a memory initialization file. To preload the memory array, perform the following steps: Open the alt_mem_if_common_ddr_mem_model_ddr3_mem_if_dm_pins_en_mem_if_dqsen.sv file. Create a memory initialization file with the following address & data format. The address & data are hexadecimal values, and the address does not need to be contiguous. @0000 DEADBEEF @0001 FEEDFACE @0104 01234567 Set the MEM_INIT_EN parameter to 1 to enable memory preloading. Set the MEM_INIT_FILE parameter to the path of the memory initialization file. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']