Synchronizing aclr with rdclk and wrclk Causes a Recovery Timing Violation in the DCFIFO IP that Connects to MLAB - Synchronizing aclr with rdclk and wrclk Causes a Recovery Timing Violation in the DCFIFO IP that Connects to MLAB Description If your design uses MLAB as RAM block type and you select the add circuit to synchronize aclr with wr/rdclk option in the Dual Clock FIFO (DCFIFO) IP Parameter Editor GUI, the read clock domain-synchronized aclr signal erroneously connects to the top-level aclr signal, instead of connecting to the MLAB\'s clr signal. This issue affects the Quartus ® Prime Standard Edition software and the Quartus Prime Pro Edition software. Resolution Instead of selecting the add circuit to synchronize aclr with wr/rdclk optioni n the DCFIFO IP Parameter Editor GUI, create your own reset synchronizer. Custom Fields values: ['novalue'] Troubleshooting FB368678; True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 16.1 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']