Why are some DDR4 signals unconstrained in the Timing Analyzer? - Why are some DDR4 signals unconstrained in the Timing Analyzer? Description You might see the following signals show up as unconstrained input and output ports in the Timing Analyzer: mem_alert_n mem_dbi_n mem_ck/mem_ck_n mem_dqs_n These signals should have false path assignments. Resolution Add the following assignments to the DDR4 SDC file under the FALSE PATH CONSTRAINTS section: set_false_path -from [get_ports {*alert_n*}] set_false_path -from [get_ports {*dbi_n*}] set_false_path -to [get_ports {*dbi_n*}] set_false_path -to [get_ports {*mem_ck*}] set_false_path -to [get_ports {*mem_ck_n*}] set_false_path -to [get_ports {*mem_dqs_n*}] This problem will be fixed in a future version of the Quartus® development software. Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1a10 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']