Can I enter negative phase shifts in the PLL Intel® FPGA IP? - Can I enter negative phase shifts in the PLL Intel® FPGA IP? Description Due to a problem in the Quartus® II Software v12.0 and earlier, the PLL Intel® FPGA IP does not support negative phase shift entry. Resolution To achieve an equivalent phase shift, add one clock cycle (360°) to any required negative phase shift so the result is a positive phase value. This problem is fixed starting with the Quartus® II Software v12.1 where the PLL Intel FPGA IP supports negative phase shift entry. Related Articles How does the PLL Usage Summary report the output clock phases for Stratix V, Arria V, and Cyclone V devices using the Altera_PLL megafunction? How do I implement ALTLVDS in External PLL Mode for Stratix V, Arria V, and Cyclone V devices? Custom Fields values: ['novalue'] Troubleshooting 2205782011 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 12.1 11.1 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']