Altera® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions - 29 Minutes This is part 5 of a 5 part course. You will learn about and how to apply the timing exceptions false paths, multicycle paths, and min and max delays using the Synopsys Design Constraints (SDC) format in the Timing Analyzer in the Altera® Quartus® Prime Pro software. Note: While the focus of this course is the Altera Quartus Prime Pro software, much of the flow and constraints are valid with the Standard and Lite versions of the software. Course Objectives At course completion, you will be able to: Apply the timing exceptions of false paths, multicycle paths, and max and min constraints Skills Required Completion of The Altera® Quartus® Prime Software: Foundation online or instructor-led course OR a working knowledge of the Altera Quartus Prime software Understanding of basic hardware timing parameters and equations used in the timing verification OR completion of Introduction to Timing Analysis If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OQPSWTMEP5. FPGA_OQPSWTMEP5. <p>Altera Quartus Prime Pro Software Timing Analysis – Part 5: Timing Exceptions</p>