How to activate loopback mode for debugging Cyclone V GX PCIe link - How to activate loopback mode for debugging Cyclone V GX PCIe link Hello I am using the PCIe-to-Avalon-MM Hard IP core in a 5CGXFC3B6U19I7 device, and I would like to enable loopback mode to debug the link between the FPGA and the processor that I am using. The FPGA is in Native endpoint mode. Can someone point me in the right direction as to how to enable loopback mode? Thank you in advance. Regards Replies: Re: How to activate loopback mode for debugging Cyclone V GX PCIe link Hi, Facing same problem in the design,Please suggest how to set that consecutive TS1 loopback bit in the root complex design.... or Please share the root complex loop back reference design. Replies: Re: How to activate loopback mode for debugging Cyclone V GX PCIe link If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Replies: Re: How to activate loopback mode for debugging Cyclone V GX PCIe link Hi, To achieve the loopback mode at the endpoint, the host may act as a loopback master, and send two consecutive TS1s with loopback bit set, so that the endpoint can enter the loopback mode. You may refer to the PCIe spec for the detailed information. Regards -SK