Verilog: Attempting to make a signal high for 5 clock cycles and then remain low - Verilog: Attempting to make a signal high for 5 clock cycles and then remain low Hello, I am trying to make the signal called ld_tx_data_scope a value of 1 after the first 5 positive edges and remain high for 5 positive edges and then have it go low and stay low. However, simulating the Verilog code provides this output for ld_tx_data_scope: As, you can see above the signal remains low. The Verilog code is shown below: module test( clk_50, ld_tx_data_scope ); input clk_50; reg ld_tx_data; output reg ld_tx_data_scope; reg tx_enable; reg [7:0] my_tx_data; reg rx_enable; reg [16:0] ld_tx_counter_debug; reg ld_tx_toggle; reg [16:0] ld_tx_data_scope_uptime; initial begin tx_enable <= 1; rx_enable <= 0; my_tx_data <= 8'b01010101; end always @* begin ld_tx_data_scope = ld_tx_data; end always@(posedge clk_50) begin ld_tx_counter_debug <= ld_tx_counter_debug + 1; //rx_counter <= rx_counter + 1; if(ld_tx_counter_debug == 5 && ld_tx_toggle == 0) //5000 begin ld_tx_counter_debug <= 0; ld_tx_data <= 1; ld_tx_toggle = 1; end if (ld_tx_toggle == 1) begin ld_tx_data_scope_uptime = ld_tx_data_scope_uptime + 1; if (ld_tx_data_scope_uptime == 5)//100 begin ld_tx_data <= 0; ld_tx_data_scope_uptime = 0; end end end endmodule I have also attached the project files. Any help is appreciated. Thanks Replies: Re: Verilog: Attempting to make a signal high for 5 clock cycles and then remain low Hi, Any further update or concern? Thanks, Best regards, Sheng Replies: Re: Verilog: Attempting to make a signal high for 5 clock cycles and then remain low Hi, Because you haven't initialize the reg ld_tx_toggle . If you had initialized like this reg ld_tx_toggle = 1'b0; You'll get correct simulation like pic below: Thanks, Best regards, Sheng p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer. Replies: Re: Verilog: Attempting to make a signal high for 5 clock cycles and then remain low Indeed. Asking your questions in this online forum ... https://www.eevblog.com/forum/fpga/ ... might get you much better results. Replies: Re: Verilog: Attempting to make a signal high for 5 clock cycles and then remain low Hi Frank, There are numerous problems in your Verilog code, but this is not an appropriate place for this query. This forum is meant for discussions on issues pertaining to Quartus software. The problems you're having are with basic Verilog programming, having nothing to do with Quartus in particular. I'd suggest you begin with a good primer course or book to learn the fundamentals of RTL design and the Verilog language. -Roee