Mentor Verification IP BFMs violate the AMBA AXI and ACE Protocol Specification - Mentor Verification IP BFMs violate the AMBA AXI and ACE Protocol Specification Description The Mentor® Verification IP (VIP) Altera® Edition AXI3™, AXI4™ and AXI4-Lite™ master bus functional models (BFMs) violate the AMBA® AXI and ACE Protocol Specification when you use the default setting write_data mode (AXI4_DATA_AFTER_ADDRESS). The AXI4_DATA_AFTER_ADDRESS mode is programmed so the master sends a valid address by asserting AWVALID. It does not send valid data (WVALID) before the address is accepted (AWREADY). The master should not wait for the slave to assert AWREADY or WREADY before asserting AWVALID or WVALID. Resolution You must set the write mode by writing <bfm>.set_write_data_mode (AXI<variable>_DATA_WITH_ADDRESS). Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']