Which signal of the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP should be used to determine when it's safe to start interacting with the AXI bus interface? - Which signal of the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP should be used to determine when it's safe to start interacting with the AXI bus interface? Description When using the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP, you may see the AXI wready signal getting asserted during calibration but it is not safe to interact yet. You should wait until the local_cal_success signal gets asserted before you start interacting with the AXI bus interface. Resolution This information will be included in a future release of the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide. Custom Fields values: ['novalue'] Troubleshooting 22013060483 False ['High Bandwidth Memory (HBM2) Interface IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 20.4 ['Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA'] ['novalue'] ['novalue'] ['novalue']