How do I use the refclock_status signal on the Agilex™ 7 F-Tile Reference and System PLL Clocks FPGA IP in Quartus® Prime Pro Edition Software version 23.2? - How do I use the refclock_status signal on the Agilex™ 7 F-Tile Reference and System PLL Clocks FPGA IP in Quartus® Prime Pro Edition Software version 23.2? Description The refclock_status output signal on the Agilex™ 7 F-Tile Reference and System PLL Clocks FPGA IP in Quartus® Prime Pro Edition Software version 23.2 is non-functional. Resolution You should not use the refclock_status output signal. If you want to know the status of your System PLL reference clock, you can infer this by monitoring whether the out_systempll_synthlock_[n] tx_pll_locked[n], tx_ready[n], and rx_ready[n] signals assert high. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.3. Custom Fields values: ['novalue'] Troubleshooting 18030480099 False ['F-Tile Reference and System PLL Clocks IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']