Simulation of the 10GBASE-R IP Core Fails in NCSim VHDL - Simulation of the 10GBASE-R IP Core Fails in NCSim VHDL
Description Simulation fails when using ModelSim with mixed-languages. Resolution The workaround is to use the -namemap_mixgen option with the ncelab command. This issue will be fixed in a future release of the Quartus II software.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
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11.0
['Programmable Logic Devices']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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