Why does the transmitter jitter increase when resetting adjacent transceiver channels? - Why does the transmitter jitter increase when resetting adjacent transceiver channels? Description You may observe increased jitter on an active transmitter channel with CMU PLL while resetting adjacent transceiver channels. This problem is caused when the CMU PLL high speed serial clock is enabled or disabled simultaneously on the adjacent channels, which causes a sudden local increase in the current consumption and jitter on the active transmitter channel. Resolution To work around this problem, use ATX PLL or fPLL instead of CMU PLL. This problem will not be fixed in a future release of the Intel® Quartus® Prime Edition versions. Custom Fields values: ['novalue'] Troubleshooting 1408163359 False ['Transceiver CMU PLL Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.0 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']