Signal Tap Logic Analyzer: State-Based Triggering, Compilation, & Programming - 37 Minutes This training is part 3 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training discusses the state-based triggering flow and the process of compiling a project that includes a logic analyzer instance. This includes a discussion of features and options for minimizing or completely avoiding recompilation time when changes are made to the logic analyzer. The training also shows you how to program a device in preparation for data acquisition and analysis. Course Objectives At course completion, you will be able to: Understand the differences between the sequential and state-based triggering flows and set up a state-based triggering flow Compile a project that includes a Signal Tap logic analyzer instance Preserve signal nodes through the compilation process for ease-of-use in debugging Perform a Rapid Recompile or ECO compile to save time when making changes to Signal Tap nodes Skills Required Basic knowledge of the Quartus Prime software knowledge of external logic Analyzer operations (optional) If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSW1172. FPGA_ODSW1172. <p>Signal Tap Logic Analyzer: State-Based Triggering, Compilation, & Programming</p>