Why do I see timing violations in my design with JTAG-Over-Protocol FPGA IP? - Why do I see timing violations in my design with JTAG-Over-Protocol FPGA IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, you might see timing violations in SignalTap-related nodes when your design includes the JTAG-Over-Protocol FPGA IP. Resolution To work around this problem, download the SDC file: auto_fab_constraints.sdc and include it in your project. This problem is fixed in version 24.3.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15012467256 False ['JTAG-Over-Protocol IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']