10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design - TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. Missing Link Electronics (MLE) is a Silicon Valley-based technology company with offices in Germany. We have been enabling key innovators in the automotive, industrial, test and measurement markets… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Cyclone® 10 GX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Defense Medical Transportation 10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design Key Features Highly modular TCP/UDP/IP stack implementation in synthesizable HDL Offering Brief No No No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Cyclone® 10 GX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes No 25.1.1 Offering Brief Production a1JUi0000049UJTMA2 What's Included Modular and application-specific 10/25G IP Core, and example design projects Ordering Information NPAP-10-25G a1JUi0000049UJTMA2 Production Design Services Intellectual Property (IP) a1MUi00000BO8sfMAD a1MUi00000BO8sfMAD Select 2026-04-21T12:58:32.000+0000 TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. Partner Solutions