Why does PCIe LTSSM enter Polling.Compliance (0x3) instead of L0 (0xF) state? - Why does PCIe LTSSM enter Polling.Compliance (0x3) instead of L0 (0xF) state?
Description PCI® Express LTSSM enters Polling Compliance when one of the following conditions occurs: 1. Test_in[6] is set to one 2. Incorrect pin assignments on the PCB
Custom Fields values:
['novalue']
Troubleshooting
novalue
False
['novalue']
['novalue']
novalue
novalue
['Arria® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document