AES-P: Programmable Advanced Encryption Standard Engine - The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-,… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Intel® MAX® 10 FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Filters /Transforms Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless AES-P: Programmable Advanced Encryption Standard Engine Key Features The NIST-validated core realizes the AES Block Cipher Algorithm, according to the NIST Federal Information Processing Standard (FIPS) Publication 197. Offering Brief Yes Yes No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Intel® MAX® 10 FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U7BMAU What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL, Encrypted VHDL, or FPGA netlist Ordering Information AES-P a1JUi0000049U7BMAU Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-09-28T22:35:03.000+0000 The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Partner Solutions