Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks - Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Description You may see the above warning message when you compile the generated example design of the UniPHY-based DDR3 memory controller. Resolution This warning will show up when users don't specify whether they are willing to have feedback and output paths differently. Intel ® Quartus ® will try to match both paths with the same compensation path. This warning can be fixed by setting the following QSF assignment: set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK OFF -to * Custom Fields values: ['novalue'] Troubleshooting NA False ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']