User Refresh Limitation in Arria V and Cyclone V Hard Memory Interface - User Refresh Limitation in Arria V and Cyclone V Hard Memory Interface Description This problem affects DDR2 and DDR3, QDR II, and RLDRAM II products. In the hard memory interface, when the fabric clock is configured much slower than the controller clock, the controller generates an extra acknowledge pulse as it waits for the request to be deasserted. This behavior is not seen in single-port memory controllers operating in one clock domain. Resolution This issue has no workaround. You can determine the number of extra acknowledge pulses by calculating the ratio of controller clock to user clock, and the phase difference. You can mask off the extra acknowledge pulses if they are not desired. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']