Why does the LPDRR4 EMIF IP hang when attempting to read from it when using the Agilex™ 5 AXI-4 Interface? - Why does the LPDRR4 EMIF IP hang when attempting to read from it when using the Agilex™ 5 AXI-4 Interface? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the LPDDR4 EMIF IP may hang when attempting to read from memory using the AXI-4 interface due to signals being unintentionally optimized away. Resolution To workaround this problem, add the /*synthesis dont_merge syn_preserve = 1*/ attribute to all the registers of the AXI bus driving the Trafic Generator. Custom Fields values: ['novalue'] Troubleshooting 14020238782 False ['EMIF Memory Device Description IP (DDR4)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 23.2 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']