Error(129001): Input port CLK on atom "fr_out_data_ddio", which is a twentynm_ddio_out primitive, is not legally connected and/or configured - Error(129001): Input port CLK on atom "fr_out_data_ddio", which is a twentynm_ddio_out primitive, is not legally connected and/or configured Description Due to a problem, the Quartus® Prime Pro Edition Software version 18.0 Update 1, this error message may be seen in a design that includes a GPIO Intel® FPGA IP instance. This problem occurs when the clock signal for the IP is connected to a clock source that is being generated from a module defined as a netlist database. The problem occurs because the software is unable to validate the origin of the source clock when it comes from an imported netlist on the design's root partition. Resolution To work around this problem, create a design partition for the imported netlist database to pass the legality check for the GPIO IP instances. Custom Fields values: ['novalue'] Troubleshooting FB: 578904; False ['GPIO IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']