How do I connect the Intel® Arria® 10 HPS EMAC with GMII interface to an external PHY using FPGA I/O pins? - How do I connect the Intel® Arria® 10 HPS EMAC with GMII interface to an external PHY using FPGA I/O pins? Description For design in which the HPS is pin-limited, the EMAC signals can be routed through the FPGA fabric default as GMII interface and adapted to SGMII mode through soft adapter logic. Resolution The Intel® HPS GMII to TSE 1000BASE-X/SGMII PCS bridge is a soft IP core in FPGA fabric which provides logic to hook up the HPS’s EMAC GMII/MII to the Altera 1000BASE-X/SGMII PCS core for SGMII interface realization. Also, Intel® provides a reference design for this application; please refer to the A10 SGMII Reference Design - User Manual , and download the reference design project from the link: https://releases.rocketboards.org/ Custom Fields values: ['novalue'] Troubleshooting 15011996212 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.1 ['Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']