Agilex 5: Altera ace5lite CCT CSR - Agilex 5: Altera ace5lite CCT CSR I am trying to send a transaction through DMA using the Altera CCT from a streaming component in the FPGA, to SDRAM. The transfer works with a UBoot script, but in Linux no changes are registered when reading the memory the DMA should have written its transaction to. I assume it is a firewall issue. In this guide they use the Intel CCT, in which it is possible to expose the CSR register to the lwhps2fpga connector so as to inform the firewall to let such transactions pass. However, for the Intel CCT: it does not exist in 25.1, and in Qsys does not allow HDL generation in : Error: Interconnect is required but is currently not supported for the acelite interface type. So I want to set the Altera CCT CSR to see if this will allow transactions, but it is not exposed. Does anyone know how to go about doing such a thing? Or even if I am approaching this issue in the right way? Many thanks! K Replies: Re: Agilex 5: Altera ace5lite CCT CSR Hi, Please let me know if you have any query on this. Regards Tiwari Replies: Re: Agilex 5: Altera ace5lite CCT CSR Hi, This reference design with Cache Coherency Translator (CCT) Intel® FPGA IP is for the Agilex-7 device. Altera ACE5-Lite Cache Coherency Translator (CCT) FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE5-Lite interface in Agilex™ 5 SoC devices and embed the cacheability and coherency signals to the ACE5-Lite subordinate of HPS. https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-73029.html Cache Coherency Translator (CCT) Intel® FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE-Lite interface in Stratix® 10 or Agilex™ 7 SoC devices and embed the cacheability and coherency settings to the ACE-Lite subordinate of HPS. https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-22704.html Regards Tiwari Replies: Re: Agilex 5: Altera ace5lite CCT CSR It may also be because I am using the Agilex 5 ( A5ED065BB32AE4SR0 ) - what do you think? Replies: Re: Agilex 5: Altera ace5lite CCT CSR Hi, Let me check again with the custom design project. Will confirm on this again. But, this IP I can see in the example design- https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/f-series/soc/setup-use-bridges/ug-setup-use-bridges-agx7f-soc/#build-hardware-design Regards Tiwari Replies: Re: Agilex 5: Altera ace5lite CCT CSR Hi Tiwari, Here you can see that in my Quartus 25.1 downloaded version, there is no reference to the intel cache coherency translator IP. $ quartus_sh --version Quartus Prime Shell Version 25.1.0 Build 129 03/26/2025 SC Pro Edition Copyright (C) 2025 Altera Corporation. All rights reserved. Would you maybe know why? I initialised this project using the project wizard with the part A5ED065BB32AE4SR0. Many thanks, K Replies: Re: Agilex 5: Altera ace5lite CCT CSR Thanks for your response Tiwari - I will look again at this. Best, K Replies: Re: Agilex 5: Altera ace5lite CCT CSR Hi, I have tried running this below design and it is generating HDL successfully. Quartus v25.1 is also showing Intel CCT IP in Qsys. https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/f-series/soc/setup-use-bridges/ug-setup-use-bridges-agx7f-soc/#build-hardware-design Regards Tiwari