Incorrect Reset Sequence for Serial Digital Interface - Incorrect Reset Sequence for Serial Digital Interface Description Long locking time in serial digital interface (SDI) I when receiving high definition (HD) in Arria V and Stratix V devices. This issue affects the Triple-Rate video standard in 12.0. Resolution There is no workaround for this issue. This issue is fixed in ACDS patches for 12.0 and 12.1. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0 12.0 ['Arria® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']