Why does the Triple Speed Ethernet MegaCore Function not generate XOFF / XON pause frames even when the XOFF / XON registers or XOFF / XON I/O pins are asserted? - Why does the Triple Speed Ethernet MegaCore Function not generate XOFF / XON pause frames even when the XOFF / XON registers or XOFF / XON I/O pins are asserted? Description Due to an issue with the Triple Speed Ethernet MegaCore® function, XON / XOFF pause frames may not be generated if you disable the Enable MAC 10/100 half duplex support option. Resolution Turn on the Enable MAC 10/100 half duplex support option in MegaWizard™ Plug-in Manager to workaround this issue. This issue has already been fixed in the Quartus II software version 15.0.1. Custom Fields values: ['novalue'] Troubleshooting 151073 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus II Software'] 15.0.1 13.0 ['Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']