Why are there timing violations on the *pld_fpll_shared_direct_async_out_hioint[2] clock domains within the Agilex™ 7 device F-Tile PMA/FEC Direct PHY Multirate FPGA IP? - Why are there timing violations on the *pld_fpll_shared_direct_async_out_hioint[2] clock domains within the Agilex™ 7 device F-Tile PMA/FEC Direct PHY Multirate FPGA IP? Description Due to a problem with the Agilex™ 7 device F-Tile PMA/FEC Direct PHY Multirate FPGA IP in the Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see timing violations on the following clock transfers: From Clock: *_auto_tiles|*__reset_controller_src_divided_osc_clk To Clock: *_auto_tiles|*|hdpldadapt_tx_chnl_*|pld_fpll_shared_direct_async_out_hioint[2] Resolution Violations between these clock domains are invalid and can be avoided using a set_false_path command. This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18027365143 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 22.4 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']