Cyclone® 10 LP FPGA Overview - Cyclone® 10 LP FPGA is optimized for low static power, low-cost applications such as I/O expansion. Product Pages Consumer Industrial Transportation Overview The Cyclone 10 LP FPGA extends the Cyclone FPGA series leadership in low-power devices targeted for high-volume and cost-sensitive applications. Cyclone 10 LP FPGA Product Table Benefits Ideal for high-volume, cost-sensitive functions, the Cyclone 10 LP FPGA is designed for a broad spectrum and suits smart and connected end applications across many market segments. Half the Power at Half the Cost All Cyclone 10 LP FPGAs require only two core power supplies for operation, simplifying your power distribution network and saving you board costs, board space, and design time. This enables you to design a lower cost system. Lower Your System Costs Built on a power-optimized 60 nm process, the Cyclone 10 LP FPGA extends the low-power leadership of the previous-generation Cyclone V FPGA. The latest generation devices reduce core static power by up to 50 percent compared with the previous generations. Reduce Power Consumption Key Features Each embedded multiplier block in the devices supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. Cascade multiplier blocks to form wider or deeper logic structures. Embedded Multipliers The logic array block (LAB) consists of 16 logic elements (LEs), each with four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables. Logic Elements and Logic Array Blocks The embedded memory structure consists of M9K memory blocks columns. Each M9K memory block of on the device provides 9 Kb of on-chip memory. Embedded Memory Blocks The cyclic redundancy check (CRC) error detection feature can check for an SEU continuously, automatically confirming the accuracy of the configuration data stored in the device and alerting the system to an occurrence of a configuration error. Single Event Upset (SEU) Applications Embedded control and edge analytics Industrial Smart embedded systems Consumer Electronics Power sequencing, sensor interfacing, and control systems Automotive Dev Kits, IP, Example Designs & Software Get Started: Development Kits, IP, Example Designs and Software Dev Kit Cyclone® 10 LP FPGA Development Kit Cost-optimized kit for embedded control and logic design. IP FFT FPGA IP Cores The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor. Multi-Rate Ethernet PHY FPGA IP This IP allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G. It handles the frame encapsulation and flow of data between a client logic and Ethernet network via PCS and PMA (PHY). Example Designs FPGA Developer Site GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral. Example Design Store This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production. Software Quartus® Prime Lite Edition Design Software Documentation Documents Documentation Cyclone 10 LP FPGA Device Overview Cyclone 10 LP FPGA Product Table Cyclone 10 LP FPGA Device Data Sheet Support Resources Cyclone® 10 LP FPGA