How do I configure and implement the Altera_PLL Cascading feature? - How do I configure and implement the Altera_PLL Cascading feature? Description Compared to the conventional PLL Cascading; the Altera_PLL Cascading feature uses a dedicated cascading clock path between a pair of fPLLs to achieve better jitter performance and save global clock resources. Download this How-To document to learn Altera_PLL cascading configuration using megafunction and implementation. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Cyclone® V FPGAs and SoCs', 'Cyclone® V SE FPGA'] ['novalue'] ['novalue'] ['novalue']