Error(23721): Cannot place block ref_sys_pll_clk_i0|systemclk_f_0|x_hip|gen_refclk_fgt_bb_[8].enabled.inst in location fgt_refclk_8 because the location cannot drive to core fabric. - Error(23721): Cannot place block ref_sys_pll_clk_i0|systemclk_f_0|x_hip|gen_refclk_fgt_bb_[8].enabled.inst in location fgt_refclk_8 because the location cannot drive to core fabric. Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, "Export Refclk #8 for use in user logic" and "Export Refclk #9 for use in user logic" are shown as available options in the Agilex™ 7 F-Tile Reference and System PLL Clocks IP. Selecting either of these options will result in Error(23721) in the Logic Generation compilation stage. Resolution Exporting Refclk #8 or Refclk #9 for use in user logic is not a supported feature in Agilex™ 7 F-Tile transceivers. Refclk #1 through Refclk #7 may be used for transceiver reference clock use in user logic. This problem is resolved in the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 18035492202 False ['F-Tile Reference and System PLL Clocks IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']