What is the RGMII TX_CLK clock period timing tolerance in Arria® V Device Datasheet? - What is the RGMII TX_CLK clock period timing tolerance in Arria® V Device Datasheet? Description Due to a problem in the Arria® V Device Datasheet , the Min/Max value for the TX_CLK period is not provided in the Ethernet Media Access Controller (EMAC) timing characteristics table in the HPS specifications section. Resolution Refer to Table 1 for the Tclk Min/Max specifications. Table 1. Tclk Min/Max Specifications Symbol Description Min Typ Max Unit Tclk(1000Base-T) TX_CLK clock period 7.2 8.0 8.8 ns This problem is scheduled to be fixed in a future release of the Cyclone® V/Arria® V Device Datasheet. Custom Fields values: ['novalue'] Troubleshooting 1507170552 False ['novalue'] ['novalue'] novalue novalue ['Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']