Internal Error: Sub-system: SSC, File: /quartus/tsm/ssc/ssc_timing.cpp, Line: 459 - Internal Error: Sub-system: SSC, File: /quartus/tsm/ssc/ssc_timing.cpp, Line: 459 Description Due to a problem in the Quartus® II software version 12.0 and later, you may see this error during synthesis if you turn on timing-driven synthesis, but all the logic in the design is removed during synthesis optimization. Resolution To work around this problem, ensure that logic remains in your design after synthesis optimization or turn off timing-driven synthesis. This problem is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']