Can the MMR interface be used in conjunction with the Efficiency Monitor in the External Memory Interface Intel® FPGA IP? - Can the MMR interface be used in conjunction with the Efficiency Monitor in the External Memory Interface Intel® FPGA IP? Description Due to a restriction in the Intel® Quartus® Prime Edition Software, it is not possible to enable the Memory Mapped Configuration and Status Register (MMR) interface in conjunction with the Efficiency Monitor when implementing DDR3 or DDR4 interfaces using the External Memory Interface Intel FPGA IP for Intel® Arria® 10, Intel® Cyclone® 10 GX or Intel® Stratix® 10 devices. Enabling both options will result in an error like that shown below : Error: Interface must have an associated clock Resolution There is no planned fix for this restriction. Custom Fields values: ['novalue'] Troubleshooting 2205746451 False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software QUARTUS-ALITE', 'FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 17.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']