Test a Verilog module via System Verilog - Test a Verilog module via System Verilog Trying to test a Verilog module via System Verilog. I'm analysing the RTL Simulation and I get the error: Error (10170): Verilog HDL syntax error at Test1.sv(29) near text: "program"; expecting a description. I tried debugging it, but no results. It shows the error here after I instantiated the module I want to test. interface valid_in1 (input clk); logic din; logic res; logic out; modport dut (input clk, din, res, output out); modport tb (input out, output clk, din, res); task monitor (); while (1) begin @(posedge clk); if (din==1'b1) begin $display ("@%0dns res %b out %b din %b clk %b", $time, res, out, din, clk); end end endtask endinterface: valid_in1 module valid (valid_in1.dut din); valid_in dut (.clk(din.clk), //the verilog module instantiation .din(din.din), .res(din.res), .out(din.out)); endmodule program validprog (valid_in1.tb tin); default clocking cb @(posedge tin.clk); endclocking initial begin fork tin.monitor(); join_none tin.res <= 1; tin.din <= 0; ##10 tin.res <= 0; ##1 tin.din <= 1; ##10 tin.din <= 0; ##5 $finish; end endprogram module Test1 (); logic clk= 0; always #1 clk++; valid_in1 cin (clk); valid dut (cin); validprog tb (cin); endmodule Replies: Re: Test a Verilog module via System Verilog Worked as a charm in EDA Playground. Thank you Replies: Re: Test a Verilog module via System Verilog I checked and it seems that the 3.4 Programs construct - whereby "The program building block is enclosed between the keywords program...endprogram" , is currently Not supported in the Quartus synthesis tools. To know more about the constructs supported. You may checkout the webpages below: Verilog HDL Synthesis Support SystemVerilog Synthesis Support