Does the reset input of the UniPHY-based external memory controllers need to be synchronous to the EMIF clock domains? - Does the reset input of the UniPHY-based external memory controllers need to be synchronous to the EMIF clock domains?
Description No, the global_reset_n and soft_reset_n input signals are synchronized to the various internal clock domains of the UniPHY-based external memory controllers before being used.
Custom Fields values:
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Troubleshooting
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False
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['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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