Why do I see intermittent functional problems with the GTS AXI Streaming FPGA IP for PCI Express* after a PCIe link reset? - Why do I see intermittent functional problems with the GTS AXI Streaming FPGA IP for PCI Express* after a PCIe link reset? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you may see intermittent functional problems from the following functions and interfaces across PCIe link resets: warm reset, Secondary Bus Reset, and Link Disable. Impacted functions and interfaces: MSI and Legacy Interrupt Application Error Reporting Function Level Reset Interface Control Shadow Interface Completion Timeout Interface VF Error Flag Interface Configuration Intercept Interface Status signals (for example, p0_ss_app_serr and p0_ss_app_ltssmstate[5:0] ) Resolution Cold reset or reconfiguration of FPGA is required to recover from the erroneous state. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Errata 16023878678, 15015798335 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']