Arria 10 PCIe Hard IP Count - Arria 10 PCIe Hard IP Count I am having a problem finding the number of PCIE hard IP blocks on some of the Arria 10 devices. I am looking for a device that has the least number of pins and that still has 4 PCIe Hard IP blocks. This document only shows the maximum number of PCIe blocks, it is not broken out by package size, and I know the F34 package cannot have 4 PCIe blocks. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pt/arria-10-product-table.pdf And this one only gives me examples of which ones have a certain number of blocks ( ie GTxxNF40 has 2, GTxxUF45 has 4) https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_a10_pcie_avst-17-0.pdf Is there a document like this that explains how many Hard PCIe blocks each Arria 10 GX device has? Thanks, Tom Replies: Re: Arria 10 PCIe Hard IP Count Thanks that was very helpful, it had exactly what I was looking for. Replies: Re: Arria 10 PCIe Hard IP Count Hi Sir, You can refer to the following link, chapter 1.1 Device Transceiver Layout for more information. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf Regards -SK