What is the minimum receiver data rate supported by the low-voltage differential signaling (LVDS) SERDES FPGA IP with Agilex™ 5 devices? - What is the minimum receiver data rate supported by the low-voltage differential signaling (LVDS) SERDES FPGA IP with Agilex™ 5 devices? Description The minimum receiver data rate supported by the low-voltage differential signaling (LVDS) SERDES FPGA IP in Agilex™ 5 devices in all modes is 600Mbps, including DPA mode, non-DPA mode and soft-CDR mode. Resolution To support a data rate lower than 600Mbps, you have the option to choose DDIO mode in the GPIO FPGA IP. Custom Fields values: ['novalue'] Troubleshooting 15016002502 False ['novalue'] ['novalue'] novalue novalue ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']