Arria 10 PCIe Hard IP Core Link Disable and Secondary Bus Reset Error - Arria 10 PCIe Hard IP Core Link Disable and Secondary Bus Reset Error Description Applications using Hot Resets (In-band Resets) such as Link Disable, Link Enable or Secondary Bus Reset may see the following errors: Width reduction Unexpected Recovery Receiver error reported by link partner All of these errors occur infrequently. If your application does not use Hot Resets, these errors do not occur. Resolution There is no workaround other than avoiding Hot Resets. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']