Is the order of the Arria10 SoC HPS Direct Shared IO pins correct? - Is the order of the Arria10 SoC HPS Direct Shared IO pins correct? Description The order of HPS functions for HPS_DIRECT_SHARED_Q1_1 to HPS_DIRECT_SHARED_Q4_12 are incorrectly reflected in the Quartus II software version 14.0 A10. This impacts Arria® 10 10AS066 and 10AS057 devices. Resolution Disregard the HPS pins involving HPS_DIRECT_SHARED functions for 10AS066 and 10AS057 devices shown in the Quartus II software version 14.0a10. The correct order has been fixed in the Quartus II software version 14.0a10.1 Update 1 (14.0a10.1) and beyond. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0a10 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']