Why are TLPs being lost when using the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express? - Why are TLPs being lost when using the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.2, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express may fail to capture the pX_tx_st_eop_i signal assertion from the application logic at the Avalon® Streaming TX interface. As a result, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express will drop the Avalon® Streaming packet and will not generate the corresponding Transaction Layer Packet (TLP). The following Avalon® Streaming packet delivered to the Avalon® Streaming TX interface may not be affected by this problem. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3. Custom Fields values: ['novalue'] Errata 1509613780 True ['PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']