Why is the o_rx_pfc port enabled for longer durations than normally when generating designs at data rates between 10G-200G using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled? - Why is the o_rx_pfc port enabled for longer durations than normally when generating designs at data rates between 10G-200G using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates between 10G-200G with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution To work around this problem, disable the truncation option when PFC is enabled for designs with data rates between 10G-200G using F-Tile Ethernet Hard IP. Custom Fields values: ['novalue'] Troubleshooting 16028716932 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 25.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']