Why does Auto Upgrade fail for the Clock Control IP? - Why does Auto Upgrade fail for the Clock Control IP? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1, Auto Upgrade might fail for the Clock Control IP when the IP was originally generated for a Stratix® 10 FPGA device and is being regenerated for an Agilex™ FPGA device. Resolution To work around this problem, if you are converting a design containing the Clock Control IP from a Stratix® 10 FPGA device to an Agilex™ FPGA device, perform one of the following actions: Convert the design from Stratix® 10 FPGA to Agilex™ FPGA using the Quartus® Prime Pro Edition software version 24.3 or earlier. After the IP has been successfully regenerated for Agilex™ FPGA, you may upgrade it to version 25.1. Remove the Stratix® 10 FPGA version Clock Control IP and manually re-create it using the Agilex™ FPGA Clock Control IP (this option is the most recommended if you use an Agile™ 3 FPGA device). This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 14024719610 False ['Clock Control Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ FPGA Portfolio'] ['novalue'] ['novalue'] ['novalue']