How can the Intel Arria® 10 EMIF IP example design traffic generator be modified for a fixed data pattern? - How can the Intel Arria® 10 EMIF IP example design traffic generator be modified for a fixed data pattern? Description When generating an Intel® Arria® 10 EMIF example design, a traffic generator is implemented with a pre-defined PRBS traffic pattern. For further debugging, it may be useful to use a fixed data pattern. Resolution The default PRBS data pattern is implemented using a LFSR (Linear Feedback Shifting Register), which is located in the altera_emif_avl_tg_lfsr_wrapper.sv file. Comment out the original code and change it to the data pattern that you require (see example below). // generate // genvar i; // for (i = 0; i < NUM_LFSR; i ) // begin : lfsr_gen // altera_emif_avl_tg_lfsr # ( // .WIDTH (LFSR_WIDTH), // .SEED (SEED * (3 1) i) // ) lfsr_inst ( // .clk (clk), // .reset_n (reset_n), // .enable (enable), // .data (lfsr_data[((i 1)*LFSR_WIDTH-1):(i*LFSR_WIDTH)]) // ); // end // endgenerate always_ff @(posedge clk or negedge reset_n) begin if (!reset_n) begin lfsr_data <= 256'H00000000FFFFFFFF00000000FFFFFFFF00000000FFFFFFFF00000000FFFFFFFF; end else if (enable) begin lfsr_data <= ~lfsr_data; end end Custom Fields values: ['novalue'] Troubleshooting SPR: 11355393; False ['External Memory Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software'] novalue 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']