HLS Performance Optimization (Part 6 of 7) - 29 Minutes In the class, you will learn how to use common methodology and techniques to boost the performance of your HLS component. We will walk through the optimization process, covering interface selection, loop optimizations, memory optimizations, and data type selection. Course Objectives At course completion, you will be able to: Create a high-performance HLS Component using common optimization techniques Examine the impact of those optimizations on performance as measured in latency as reported through the cosimulation flow Skills Required Basic understanding of the C++ programming language Basic understanding of FPGAs and the Altera® Quartus Development Environment If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHLS6. FPGA_OHLS6. <p>HLS Performance Optimization (Part 6 of 7)</p>