Why are timing violations observed on the RX link of the Agilex™ 5 FPGA MIPI D-PHY IP design when using the Quartus® Prime Pro Edition Software version 24.3? - Why are timing violations observed on the RX link of the Agilex™ 5 FPGA MIPI D-PHY IP design when using the Quartus® Prime Pro Edition Software version 24.3? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, timing violations on the RX link, similar to those shown below, will be seen for Agilex™ 5 MIPI D-PHY IP designs. From node: LINK0_dphy_io_dphy_link_dn[*] To node:dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|dphy_link[*].dphy_link_used.dphy_pcs|dphy_rx.dphy_pcs_rx|dphy_pcs_dlanes[**].pcs_data_rx|rx_data_lp_n_q1 Resolution There is no workaround for this problem in the Quartus® Prime Pro Edition Software version 24.3; these failing paths can be safely ignored. This problem is fixed beginning with version 24.3.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14023384896 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']