Why does configuration of the JESD204B Intel® FPGA IP generated design example fail with Intel® Stratix® 10 TX devices? - Why does configuration of the JESD204B Intel® FPGA IP generated design example fail with Intel® Stratix® 10 TX devices? Description When targeting Intel® Stratix® 10 TX devices, the JESD204B Intel FPGA IP generated design example will not contain the correct SmartVID assignments in the project Quartus® Settings File (qsf) file. This will result in configuration failure. Resolution To work around this problem, update the SmartVID assignments in the Quartus Settings File (qsf) of the design example with the following assignments or equivalent based on your SmartVID configuration: #VID assignments set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 48 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY" set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS Custom Fields values: ['novalue'] Troubleshooting 1507163592 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']