Why is the Intel® FPGA Low Latency Ethernet 10G MAC IP not able to generate XON pause frames when priority flow control feature is enabled? - Why is the Intel® FPGA Low Latency Ethernet 10G MAC IP not able to generate XON pause frames when priority flow control feature is enabled? Description Due to a problem with the Low Latency Ethernet 10G MAC Intel® FPGA IP, XON pause frames generation may not work for multiple queues if XOFF pause frame generation for multiple queues are enabled, followed by a XON pause frame generation for a single queue. Resolution There is no workaround for this problem. This problem has been fixed starting in version 18.1 of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 567665; True ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 13.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']