Why does the Quartus II software report unconstrained paths when running quartus_sta with the --sdc option to perform timing analysis? - Why does the Quartus II software report unconstrained paths when running quartus_sta with the --sdc option to perform timing analysis? Description You may observe Quartus® II software report unconstrained paths while running quartus_sta with the --sdc option to perform timing analysis. This behavior may occur even though there are no unconstrained paths when running a full compilation. If you use the --sdc option for the quartus_sta command, the software uses only the constraints in the specified Synopsys Design Constraints ( .sdc ) file for timing analysis, but not the embedded timing constraints in your design files. Resolution To avoid this behavior, do one of the following actions: Include the command read_sdc -hdl within your specified .sdc file to have the software use the embedded constraints. Remove the --sdc option. Without the --sdc option, the software performs timing analysis using the embedded constraints in design files and the .sdc files in your project. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']